Post Quantum RISC-V Chips

Quantum systems will be able to break widely used asymmetric security protocols such as RSA or elliptical curve algorithms that protect billions of IoT devices today.

It will soon be mandatory to implement post quantum cryptography to secure your devices and IoT ecosystems.
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introduction

Quantum-proof security

Our upcoming secure chips family is based on a RISC-V Quantum Resistant and CCEAL5+ hardware platform that can be delivered open to load your firmware, or with a pre-provisioned FIPS 140-3 and TCG certified TPM stack. 
MS_600X QS 7001

QS7001

A RISC-V Secure Hardware platform offering CC EAL 5+ certified security and optimized for Kyber and Dilithium quantum resistant algorithms to face the latest attack scenarios.
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KEY FEATURES

  • 80MHz 32-bit Secured RISC-V CPU
  • CCEAL 5+ certified
  • Post Quantum: Kyber (512/768/1024) & Dilithium 2
  • RSA, ECC (572 bits), AES, DES, 3DES
  • SP 800 90 B RNG
  •  Communication: 1MBps I2C, 33MHz SPI
  • Memory: 512K Flash, 80K RAM, 128K ROM
  • 4 GPIOs, 3 Timers
  • 1,62V to 3,6V / -40° to 105° operating range
  • Package QFN32 - TPM compliant pinout
MS_600X QVault TPM

QVault TPM

The only post quantum TPM: A robust TCG certified TPM stack powered by the QS7001 quantum resistant hardware platform.
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KEY FEATURES

  • FIPS 140-3 and TCG certified
  • TCG TPM Library Spec 2.0
  • TCG 's PC Client platform
  • Quantum Resistant (Kyber / Dilithium)
  • Pre-Provisionned: 2048 bits RSA KeyPairs, Endorsement Keys & EK Certificates (RSA2048, ECC P256, ECC P384)
  • Cryptography: ECC (256 bits) 
  • Digital Sign: ECDSA    
  • Universally Recognized Root-of-Trust                

Certifications

Our Post Quantum chips family features CC EAL5+ certified tamper resistant hardware running a TCG and FIPS 140-3 certified TPM Stack that provide cryptographic services for authentication, data confidentiality and integrity check.

Logo-certificationFIPS-140-3
CCC
ISO 27001 (1)
TCG SEALSQ logo
Logo-partenaireNIST
SEAL SQ Implementing Quantum-proof algorithms in secure hardware doc

Implementing Quantum-proof algorithms in secure hardware

From 2018 to 2021 SEAL SQ quantum innovation team has co-directed a PhD thesis on the implementation of post-quantum algorithms in our secure architectures. 

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